Design and Implementation of ALU using Redundant Binary Signed Digit (2024)

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Arithmetic operations in digital signal processing applications suffer from problems including propagation delay and circuit complexity which may occupy larger area. We have two high performance methods among all ALU circuitry. First one is QSD and another one is VEDIC methodology. In QSD number representation allows a method of fast addition/subtraction because the carry propagation chains are eliminated and hence it reduces the propagation time in comparison with common radix 2 system. Here we propose an arithmetic unit based on QSD number system based on quaternary system. The proposed design is developed using VHDL and implemented on FPGA device and results are compared with conventional Vedic arithmetic unit. The implementation of quaternary addition and multiplication results in a fix delay independent of the number of digits. Operations on a small number of digits such as 8, 4, or more, can be implemented with constant delay and less complexity. Digital signal processing (DSP) is the technology that is omnipresent in almost every engineering discipline. A typical processor devotes a considerable amount of processing time in performing arithmetic operations, particularly multiplication operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. The core computing process is always a multiplication routine; therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them. Vedic mathematics is the name given to the ancient system of mathematics, which was rediscovered, from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. Keywords— QSD method, Vedic maths, VHDL, Delay, logical operation.

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The carry propagation during the addition operation limits the speed of arithmetic operations. In digital arithmetic, several approaches were proposed to provide the best implementation for addition operation of two operands with minimum carry propagation delay. As one of the major solutions for this problem is to use Signed-Digit-Adder (SDA), in which the (ith) digit of the sum is exclusively dependent on the (ith) digit. In this paper, we propose an Efficient Hardware Design and Verification of Signed-Digit-Adder for two Signed-Digit Radix-4 Operands benefiting from the inherent parallelism of the SDA's operation and the use of basic structural logic circuits at the gate level. This new design will form an adder for two singed-operands of symmetric redundant number representation system with a fixed radix-4 system. Simulation results shown that the Proposed work enhance the critical path delay of the SDA-unit by 55%.

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robina bagga

Adders are the key element of the arithmetic unit, especially fast parallel adder. Redundant Binary Signed Digit (RBSD) adders are designed to perform high-speed arithmetic operations. The RBSD Number System is gaining popularity due to the properties of carry-free addition / subtraction. In computational environment it is not convenient for manual computations but useful in designing high-speed arithmetic machines. This number system eliminates the carry / borrow propagation chains which reduces the computational time and enhances the speed of the machine. In this paper the circuit of fast RBSD adder cell proposed by Kal and Rajashekhar in 1990 and modified by N.Sharma in 2006, are designed using Hardware Discriptive Language and simulated on modelsim simulator.

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Design and Implementation of ALU using Redundant Binary Signed Digit (2024)

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